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Topic ALI1429 from EPARTS FAQ base

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Пожалуйста, обратите внимание на дату представленного здесь сообщения! Информация об адресах, телефонах, организациях и людях наверняка устарела и потеряла практическую ценность, обретя, однако, ценность историческую, заради которой до сих пор и хранится...

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— SU.HARDW.PC.MOTHERBOARD (2:5020/299)  —————————————— SU.HARDW.PC.MOTHERBOARD —
 From : Dennis Chikin                       2:5054/4.2      Sun 28 Jan 96 19:10 
 Subj : ALI1429                                                                 
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По просьбам трудящихся (избранное)

22h - index
23h - data (R/W)

03h         c5h - config. registers unlocking
            else- config& registers locking

12h
    d0      - 128K ROM
    d1      - on-board 15M range memory will not be recognized, and will be
              treated as the ISA range
    d2      - enable memory split remapping feature
    d3      - RAS signal active timeouut check
    d4      - hidden refresh
    d5      - enable active ROM chip select signal in the ROM region memory
              write cycle
    d6      - 0c0000-0c7fff ROM enable
    d7      - 0c8000-0cffff

13h
    d0      - 0c0000-0c7fff region shadow control
        ...
    d7      - 0f7000-0fffff region shadow control


14h
    d0      - shadow region read control
    d1      - shadow region write control
    d2      - Weitek coprocessor present
    d3      - 80387 present
    d6      - LDEVJ priority lower than on-board memory region

15h         - remapping solit address (A20-A27)


16h
    d1d0    - read  access memory timing
    d3d2    - write access memory timing
                00 - slow
                11 - fast
    d4      - disable bank 0
    d5      = disable bank 1
    d6      - disable bank 2
    d7      - disable bank 3

17h
    d1d0    - cycle check point select
                00 - reserved
                11 - slow (x1 only)
    d2      - enable on-board memory parity check
    d5d4    - HITMJ sampling timing definition
                00 - 2t
                11 - 6t
    d7      - L1KENJ check timing
                0 - 1-st T2 middle
                1 - T1 end

18h
    d0      - enable L1 cache
    d1      - enable L2 cache
    d2      - flush L1
    d5d4    - cache SRAM type (8*8 - 128*8)
    d6      - 2 bank L2
    d7      - snoop write back CHOLD/BOFFJ operation type
                0 - Assert CHOLD after 1-st ADSJ during HITMJ
                1 - Only assert BOFFJ after HITMJ inactive

19h
    d0      - L2 miss
    d1      - L2 read cycles NON-DIRTY
    d2      - L1 WB
    d3      - L2 WB
    d4      - L1 < 16M WB
    d5      - Write long
    d6      - read long
    d7      - force L2 hit

1ah

    d0      - enable L2 cacheable shadow region code accsess & set
              to be write protect
    d1      - enable data access & set to be write protect
    d2      - enable L1 cacheable shadow region code access & set WT
    d3      - enable data access $ set WT


    d5d4    - HitMJ inactive to IOCHRDYJ inactive
                00 - 2t
                11 - 6t
    d7d6    - Non CPU RAS/CAS
                01 - 2t
                11 - 6t

1eh
    d0      - IOCHRDY asserted in ISA master command low cycle
    d1      - Extend the internal ISA master command high time
    d2      - L2 VESA master cycle write long
    d3      - L2 VESA read long
    d4      - VESA master delay ADSJ

20h
    d2d1d0  - AT clock:
                111- reserved
                000 - 7.19Mhz
                ... - clk2/4,5,6,8,10,12
    d3      - host address A31-A16 "1" ROM select decoder feature enabled
    d6d5d4  - polling clock:
                000 - 14.318
                001 - clk2
                ...   clk2/2,3,4
                101 - 28.636


22h
    d0      - io recovery
    d1      - chip recovery
    d2      - ISA write end insert wait
    d7d6d5d4- recovery period (.25uS step)

25h
    d1d0    - ISA I/O insert wait
    d3d2    - ISA mem insert wait
    d5d4    - refresh period (30-120uS)
    d7d6    - 32-bit ISA insert (2-8t)

27h
    d0      - local device (NP) ready sin. mode setting
                0 - syn. L(NP)RDY to CPURDY(RDYRTN)
                1 - combination bypass L(NP)RDY to CPURDY(RDYRTN)
    d1      - enable delay internal ADSJ
    d2      - L2 cache write hit CWEJ pulse setting in 386 system
                1 - enable CWEJ delay tail rising edge
    d3      - software SMIACKJ (CPU without SMI)
    d5d4    - delay ISA cycle LDEVJ check point
    d7d6    - TAGWEJ delay rising timing setting

Остальное набивать ломы, да и нафиг не нyжно.

--- Хороший дед - голый
 * Origin: Non system tormoz  (2:5054/4.2)

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