Topic 82391 from EPARTS FAQ base
Пожалуйста, обратите внимание на дату представленного здесь сообщения! Информация об адресах, телефонах, организациях и людях наверняка устарела и потеряла практическую ценность, обретя, однако, ценность историческую, заради которой до сих пор и хранится...
— SU.HARDW.PC.MOTHERBOARD (2:5020/140.13) ——————————— SU.HARDW.PC.MOTHERBOARD — From : Vitalic Zagorodnuk 2:5020/168.300 Tue 19 Oct 93 17:26 Subj : 82.391.dsk ———————————————————————————————————————————————————————————————————————————————— Для известной матеpи MB-321 я составил некое опписание чипсета. В нем есть пpобелы - ну не вините что смог сделать без описания то сделал. Пpи составлении сего документа использовалась дока для LastBytа, Tasm 3.0, SST и MB321... { PCCHIP4 provides 192k of memory in twelve 16k blocks between C0000-EFFFF. (RAM=C000:12x16k, ROM=C000:3x64k) PCCHIP4 is functionally identical to the OPTi Electronics 82C391 and the Atmel AT40391. Access to any of the configuration registers is done first by writing the index of the desired register into IO port 22h and then followed by an access (either read or write) to IO port 24h for the data. All the configuration registers are reset to 0 at power up. Bits Definition of Configuration Registers Register 0 (index=20)=02 bit 0,1,2,3,4,5 ??? bit 6 0 Always bit 7 0 Always 02 = M321 00 = M320 Register 1 (index=21)=79 bit 0 cache write wait state 0 1 WS 1 0 WS bit 1 cache size 0 32K*8 1 8K*8 bit 2,3 ??? bit 4 External cache control 1 Enable 0 Disable bit 5 Parity check 0 Enable 1 Disable bit 6,7 ??? Register 2 (index=22)=78 bit 0,1,2 ??? bit 3 Segment E0000-EFFFF protection 0 Read/Write 1 Read only bit 4 Segment D0000-DFFFF protection 0 Read/Write 1 Read only bit 5 BIOS from E0000-EFFFF control 1 Memory 0 ROM from ATbus bit 6 BIOS from D0000-DFFFF control 1 Memory 0 ROM from ATbus bit 7 Main BIOS shadow control 0 Enable 1 Disable Register 3 (index=23) Shadow control register for segments D0000-EFFFF bit 0 Memory address from D0000h to D3FFFh bit 1 Memory address from D4000h to D7FFFh bit 2 Memory address from D8000h to DBFFFh bit 3 Memory address from DC000h to DFFFFh bit 4 Memory address from E0000h to E3FFFh bit 5 Memory address from E4000h to E7FFFh bit 6 Memory address from E8000h to EBFFFh bit 7 Memory address from EC000h to EFFFFh 0 Disable shadow (default) 1 Enable shadow When a bit is set to 0, access to the address within the specified memory block is directed to the ATbus. When a bit is set to 1, access to the address within the specified memory block is directed to the local DRAM. Register 4 (index=24)=8F Memory configuration 8F - 1*4 = 4Mb 9F 1*4+1*4= 8Mb 0F,1F = 256*4=1Mb 97 = 8Mb Register 5 (index=25)=47 Memory control bit 0 1 Always bit 1 1 Always bit 2 1 Always bit 3 1 Always bit 4,5 Memory write wait state bit5 bit4 0 0 0 WS 0 1 1 WS 1 0 2 WS 1 1 3 WS bit 6,7 Memory read wait state bit7 bit6 0 1 0 WS 1 0 1 WS 1 1 2 WS Register 6 (index=26)=BF Shadow control register for segments C0000-CFFFF bit 0 Memory address from C0000h to C3FFFh bit 1 Memory address from C4000h to C7FFFh bit 2 Memory address from C8000h to CBFFFh bit 3 Memory address from CC000h to CFFFFh 0 Disable shadow (default) 1 Enable shadow When a bit is set to 0, access to the address within the specified memory block is directed to the ATbus. When a bit is set to 1, access to the address within the specified memory block is directed to the local DRAM. bit 4 1 always bit 5 BIOS control 0 Memory 1 ROM from ATbus bit 6 Segment protection 0 Read/Write 1 Read only bit 7 ??? Register 7 (index=27) bit 0,1,2,3 ??? bit 4 Video cacheble C0000-C7FFF 0 Enable 1 Disable bit 5 1 Always bit 6 1 Always Register 8 (index=28)=9C bit 0,1 Non-cacheble block 1 base high address bit0 bit1 0 0 0 0 1 16384Kb 1 0 32768Kb bit 2 1 Always bit 3 1 Always bit 4 1 Always bit 5,6 Non-cacheble block 1 size bit6 bit5 0 0 64Kb 0 1 128Kb 1 0 256Kb 1 1 512Kb bit 7 Non-cacheble block 1 control 0 Enable 1 Disable Register 9 (index=29)=00 bit 0,1,2 ??? bit 3,4,5,6,7 Non-cacheble block 1 base low address b7 b6 b5 b4 b3 0 0 0 0 0 0 0 0 0 0 1 512Kb 0 0 0 1 0 1024Kb 0 0 1 0 0 2048Kb 0 1 0 0 0 4096Kb 1 0 0 0 0 8192Kb Register A (index=2A) Non-cacheble block 2 control equivalent 28 Register B (index=2B) Non-cacheble block 2 base address equivalent 29 } Если что непpавильно пишите на оpижин... ыitalic, ;-F --- Yet another GoldED 2.41+ * Origin: SBS-Net, Moscow, Russia (2:5020/168.300)
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