Topic 8042 from EPARTS FAQ base
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— RU.HACKER (2:5020/75.7) ————————————————————————————————————————— RU.HACKER — From : Andrew Cuzin 2:5030/33 Mon 13 Sep 93 15:37 Subj : Keyboard commands & interface ———————————————————————————————————————————————————————————————————————————————— Keyboard controller. The keyboard controller is 8742 single chip microcomputer-based and is used to support 386 PC keyboard interface. The controller has the following functions: - receive serial data from the keyboard, check parity of the data and translate it to system scan code, if necessary. Put the received and processed data into the data buffer and interrupt processor. - execute system commands through the controller command buffer and place the result, if necessary, in the data buffer and interrupt the processor. - transmit system data, placed in the data buffer, to the keyboard in a serial format with the parity bit inserted. Get the response from the keyboard and report to the system. - report any error to the system through status register at the time of data communication with the keyboard. Receiving data from the keyboard. The keyboard sends data in an 11-bit serial format. The first bit is a start bit (low level) followed by 8 data bits (LSB first), an odd parity bit and stop bit (high level). Data sent is synchronized with keyboard clock. Upon receiving a byte of data from the keyboard, the keyboard controller places the data in its one byte receive-data buffer and disables the keyboard interface until that data is picked up by the system processor. This avoids data overrun. On parity error, the controller requests the keyboard to resend the data. If the error is repeated, the controller sets the parity error bit in its status register. Timeout error is indicated by setting timeout bit in the status register, if all the 11 bits are not received within 2 millisecods from start of transmission. In case of either of these errors, hex FF is placed in the receive-data buffer. Sending data to the keyboard. Data is sent to keyboard in the same serial format as data received from the keyboard. If the time between request to send and start of transmission is greater than 15 milliseconds, or if the duration of transmission is greater than 2 milliseconds, the transmit timeout error bit is set in the status register. The keyboard is required to acknowledge every transmission from the controller. If the acknowledgement has parity error, then controller sets both parity and transmit timeout error status bits. Also, if the acknowledgement does not arrive within 25 milliseconds, both receive and transmit timeout error bits are set. In case of all these errors, hex FF is placed in the data buffer. No reties are made for error at the time of transmitting to the keyboard. Keyboard inhibit. The keyboard can be inhibited through keylock jumper. When the keyboard is inhibited, although all transmissions from the system to the keyboard will be allowed, the keyboard controller tests all data received from the keyboard. If it is a response to a command sent to the keyboard, then it is placed in the data buffer, otherwise it is ignored. Keyboard controller system interface. The system communicates with the keyboard controller through an input buffer, an output buffer and a status register. The status register can be read through I/O port 64h. The output buffer can be read through I/O port 60h. The input buffer can be written through both I/O ports 60h and 64h. When the input buffer is written through I/O port 64h, the controller interprets it as a command and if it is written through I/O port 60h, then the data is interpreted either as a parameter to a command to the controller or a data to be transmitted to the keyboard. Keyboard controller status register (KB$CSR) bit definitions. 0 - Output buffer full. A 0 indicates that the keyboard controller's output buffer has no data. When the keyboard controller writes to the output buffer, this bit is set to 1. It returns to 0, when the system reads the output buffer (60h). 1 - Input buffer full. A 0 indicates that the keyboard controller's input buffer (60h or 64h) is empty. When the system writes to the input buffer, this bit is set to 1. It gets reset to 0 when controller reads the input buffer. 2 - System Flag. The keyboard controller can set this bit to 0 or 1 depending on the command from the system.It is set to 0 after power on reset. 3 - Command/Data. This bit is used by the keyboard controller to determine whether the input buffer contains the command or data. When the system writes to the input buffer through i/O port 64h, this bit is set to 1. When system write to the input buffer, this bit is set to 0. 4 - Inhibit Switch. This bit reflects the state of the keyboard inhibit switch. This bit is updated whenever the controller writes to the output buffer. A 0 indicates that the keyboard is inhibited. 5 -Transmit Timeout. A 1 indicates that a data transmission form the keyboard controller to the keyboard was not properly completed within the predefined time limit. 6 - Receive Timeout. A 1 indicates that a data transmission from the keyboard to the keyboard controller was not properly completed within the predefined time limit. 7 - Parity Error A 1 indicates that the last byte received from keyboard had a parity error. The keyboard sends data with odd parity. Keyboard controller I/O ports. The keyboard controller has two 8-bit I/O ports one of which is used as an input port & the other as an output port. The following tables show bit definitions for the I/O pot\rts and test input ports. Input port definitions. bit 0 - bit 3 Undefined bit 4 RAM on system board: 0 - 256k total on-board RAM 1 - 512k or greater on-board RAM bit 5 Undefined bit 6 Display type switch: 0 - Primary color 1 - Primary mono bit 7 Keyboard inhibit switch: 0 - keyboard inhibited 1 - keyboard not inhibited Output port definitions. bit 0 Reset to system processor (software should keep it 1 for CPU to work) bit 1 Gate A20 of CPU: 0 - CPU A20 line is inhibited on system bus. A20 will remain zero for any system bus cycle. 1 - CPU A20 line is not inhibited. bit 2 Undefined bit 3 Undefined bit 4 Output buffer full interrupt to the system bit 5 Input buffer full interrupt to the system bit 6 Keyboard clock (output) bit 7 Keyboard data (output) System commands to keyboard controller (I/O address 64h) 020h Read keyboard controller's command byte. The controller sends its current command byte to its output buffer. 060h Write keyboard controller's command byte. The next byte of data supplied by the system is the controller's commands byte, which is written to I/O port 60h. Bit definitions as follows: 0 - Enable output buffer full interrupt. 1 - enable/ 0 - disable. 1 - Not used. 2 - System Flag. Keyboard controller writes value written in this bit to bit 2 of KB$CSR. 3 - Inhibit Override. Writing 1 to this bit disables the keyboard inhibit function through keyboard clock. 4 - Disable keyboard. When set to 1, this disables the keyboard interface by driving the 'clock' line low. 5 - Reserved. Must be 0 for proper operation. 6 - IBM PC compatibility mode. When this bit is set, the controller converts the scan code received to the IBM PC compatible scan code. This includes the two byte break sequence received from IBM PC/AT compatible keyboard to the one byte IBM PC break code format 4. 7 - Not used. 0AAh Self Test. This commands the controller to perform internal diagnostic. The controller returns 055h to the output buffer if no error is detected. 0ABh Interface Test. This commands the controller to test keyboard clock & data lines. The test result placed in the output buffer is as follows: 00 - No errors detected. 01 - Keyboard clock line stuck low. 02 - Keyboard clock line stuck high. 03 - Keyboard data line stuck low. 04 - Keyboard data line stuck high. 0ACh Diagnostic Dump. Upon receiving this command the controller returns the contents of its 16 registers, the current state of input port, the current state of output port and its PSW content. All items are send in scan code format. 0ADh Disable Keyboard Interface. This command disables the keyboard interface by driving the clock line low. It also set bit 4 of the KB$CSR. 0AEh Enable Keyboard Interface. This command enables the keyboard interface and also clears bit 4 of KB$CSR. 0C0h Read Input Port. This commands to the keyboard controller to read the input port and place the data in the output buffer. 0D0h Read Output Port. This commands to the keyboard controller to read the output port and place the data in the output buffer. 0D1h Write Output Port. This command is used to write the data given through port 60h to output port. Ensure that the output port bit 0 is not written as it is connected to the reset of CPU. 0E0h Read Test Inputs. Upon receiving this command the controller reads its T0 and T1 inputs and places the data in the output buffer. Data bit 0 represents T0 and bit 1 represents T1. 0F0h-0FFh Pulse output port. Bit 0 through 3 of output port can be pulsed for approximately 6 microseconds by this command. Bit 0 through 3 of this command indicates which bits of the output port are to be pulsed. A 0 indicates that the bit is to be pulsed and a 1 indicates that the bit is to be unmodified. Note that bit 0 of output port is connected to CPU reset, so CPU can be reset by pulsing this bit. Keyboard controller keyboard interface. The keyboard controller communicates with the keyboard over a clock line (bit 6 of the output port) and the data line (bit 7 of the output port). The keyboard controller reads the data line through a test input T1 and the clock line line through a test input T0. For any type of data transmission with the keyboard, the keyboard clock is used. Data is made available after the rising edge of the clock and is sampled on the falling edge. --------------------------8<--------------------------------- Copyright (c) 1990 by American Megatrends, Inc. Extracted from SL-386/Series 5 (with 82C206) motherboard descripion. Kludge --- GoldED 2.41+ * Origin: * SoftScribe BBS * +7(812)272-6559 * 22.00-9.00 * HST * (2:5030/33)
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